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<title>DM-CtrlH7-BF-DevProgram: Class Members - Variables</title>
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   <div id="projectname">DM-CtrlH7-BF-DevProgram<span id="projectnumber">&#160;beta 0.1</span>
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   <div id="projectbrief">C.ONE Studio Damiao Development Board Framework</div>
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<div class="contents">
<div class="textblock">Here is a list of all documented variables with links to the class documentation for each member:</div>

<h3 class="doxsection"><a id="index_s" name="index_s"></a>- s -</h3><ul>
<li>Sai1ClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#adc2a83ae9e108a3f7afb01c58f3a4f1a">RCC_PeriphCLKInitTypeDef</a></li>
<li>SCAR_CUR1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a77560cf333f29a0136bc491b71bcfb14">FLASH_TypeDef</a></li>
<li>SCAR_PRG1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a51b63ab13930aa7ec22de3d337e0174a">FLASH_TypeDef</a></li>
<li>SCR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga3a4840c6fa4d1ee75544f4032c88ec34">SCB_Type</a></li>
<li>SDCMR&#160;:&#160;<a class="el" href="struct_f_m_c___bank5__6___type_def.html#ad328f49a71561cd3f159af6faf65a641">FMC_Bank5_6_TypeDef</a></li>
<li>SDCR&#160;:&#160;<a class="el" href="struct_f_m_c___bank5__6___type_def.html#a252c4ada37ac883b8e4fe0b08c781d0b">FMC_Bank5_6_TypeDef</a></li>
<li>SdmmcClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#a84a697c2eb8ce0f3e74619aa2bfc1a2d">RCC_PeriphCLKInitTypeDef</a></li>
<li>SDRTR&#160;:&#160;<a class="el" href="struct_f_m_c___bank5__6___type_def.html#ac1887d031d16c1bf2c0a51ee9001f886">FMC_Bank5_6_TypeDef</a></li>
<li>SDSR&#160;:&#160;<a class="el" href="struct_f_m_c___bank5__6___type_def.html#a9f268f86cf706c2c78d8a6a9fbe9d9a3">FMC_Bank5_6_TypeDef</a></li>
<li>SDTR&#160;:&#160;<a class="el" href="struct_f_m_c___bank5__6___type_def.html#a8438638391415aaa0dc96714f28915ae">FMC_Bank5_6_TypeDef</a></li>
<li>Sector&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___c_r_c_init_type_def.html#abca61b78540e8669315a39d65bca3271">FLASH_CRCInitTypeDef</a>, <a class="el" href="struct_f_l_a_s_h___erase_init_type_def.html#a13bac8f9a1ba504a265b44345ecf4d2b">FLASH_EraseInitTypeDef</a>, <a class="el" href="struct_f_l_a_s_h___process_type_def.html#a0c9115ac01c2fefd3c6ad112e7133b29">FLASH_ProcessTypeDef</a></li>
<li>SecureAreaConfig&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___o_b_program_init_type_def.html#a415be39a396d41f4c8f2ebbb78a5779c">FLASH_OBProgramInitTypeDef</a></li>
<li>SecureAreaEndAddr&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___o_b_program_init_type_def.html#aab19457e9f329c653db2dabf771dda3d">FLASH_OBProgramInitTypeDef</a></li>
<li>SecureAreaStartAddr&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___o_b_program_init_type_def.html#a655813b01114752ce1dda79eb0b57561">FLASH_OBProgramInitTypeDef</a></li>
<li>SFCR&#160;:&#160;<a class="el" href="group___c_m_s_i_s___core___sys_tick_functions.html#ga82273352d2e8c7a28a7b7cbdfc3d6a75">SCB_Type</a></li>
<li>SFPA&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gadab539fdfb991718401475bf6853669c">CONTROL_Type</a></li>
<li>SHCSR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga7b5ae9741a99808043394c4743b635c4">SCB_Type</a></li>
<li>SHHR&#160;:&#160;<a class="el" href="struct_d_a_c___type_def.html#a7c409f086ada3e148621979f7a0267ac">DAC_TypeDef</a></li>
<li>SHIFTR&#160;:&#160;<a class="el" href="struct_r_t_c___type_def.html#a6082856c9191f5003b6163c0d3afcaff">RTC_TypeDef</a></li>
<li>SHP&#160;:&#160;<a class="el" href="group___c_m_s_i_s___core___sys_tick_functions.html#ga5c40d124f95a3f7f431a3d5409d6ad28">SCB_Type</a></li>
<li>SHPR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga9a442e7582573585ee0489267450dedb">SCB_Type</a></li>
<li>SHRR&#160;:&#160;<a class="el" href="struct_d_a_c___type_def.html#ad2cd6f3c7ab07ff01b38155f94830c06">DAC_TypeDef</a></li>
<li>SHSR1&#160;:&#160;<a class="el" href="struct_d_a_c___type_def.html#ab0a6020e38c6ea1bf6c23311cd24b1ea">DAC_TypeDef</a></li>
<li>SHSR2&#160;:&#160;<a class="el" href="struct_d_a_c___type_def.html#a7d16719e4c287e32872eb5fec7bed27c">DAC_TypeDef</a></li>
<li>SIDFC&#160;:&#160;<a class="el" href="struct_f_d_c_a_n___global_type_def.html#a4496cb1d1555878c1490e8992f2bb2bc">FDCAN_GlobalTypeDef</a></li>
<li>SIDR&#160;:&#160;<a class="el" href="struct_p_s_s_i___type_def.html#abdcc7e0e2d580f161ccdd7a0f012271d">PSSI_TypeDef</a></li>
<li>sigma&#160;:&#160;<a class="el" href="structarm__gaussian__naive__bayes__instance__f32.html#a79faff64822a9995817add968862212d">arm_gaussian_naive_bayes_instance_f32</a></li>
<li>SignalID&#160;:&#160;<a class="el" href="struct_h_a_l___d_m_a___mux_request_generator_config_type_def.html#aff395dffdb21bf54d97d82cf0982648a">HAL_DMA_MuxRequestGeneratorConfigTypeDef</a></li>
<li>signals&#160;:&#160;<a class="el" href="structos_event.html#ad63c33b8b5d3bb37b45433d7c67d1e09">osEvent</a></li>
<li>Sint&#160;:&#160;<a class="el" href="structarm__rfft__fast__instance__f32.html#a37419ababdfb3151b1891ae6bcd21012">arm_rfft_fast_instance_f32</a>, <a class="el" href="structarm__rfft__fast__instance__f64.html#af8b9e88d37989d746cd3ced9663f4bb0">arm_rfft_fast_instance_f64</a></li>
<li>SlaveMode&#160;:&#160;<a class="el" href="struct_t_i_m___slave_config_type_def.html#a2792de155698128ade1e505618c1bc43">TIM_SlaveConfigTypeDef</a></li>
<li>SLEEPCNT&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga416a54e2084ce66e5ca74f152a5ecc70">DWT_Type</a></li>
<li>SLOTR&#160;:&#160;<a class="el" href="struct_s_a_i___block___type_def.html#aaef957d89b76c3fa2c09ff61ee0db11d">SAI_Block_TypeDef</a></li>
<li>SMCR&#160;:&#160;<a class="el" href="struct_t_i_m___type_def.html#a67d30593bcb68b98186ebe5bc8dc34b1">TIM_TypeDef</a></li>
<li>SMPR1&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a73009a8122fcc628f467a4e997109347">ADC_TypeDef</a></li>
<li>SMPR2&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a9e68fe36c4c8fbbac294b5496ccf7130">ADC_TypeDef</a></li>
<li>Source&#160;:&#160;<a class="el" href="struct_r_c_c___c_r_s_init_type_def.html#aea4064c542d29150a92632119b8e214d">RCC_CRSInitTypeDef</a></li>
<li>SourceBlockAddressOffset&#160;:&#160;<a class="el" href="struct_m_d_m_a___init_type_def.html#a0fa6c85fbcd124d36b6a9ff7bc33bd76">MDMA_InitTypeDef</a></li>
<li>SourceBurst&#160;:&#160;<a class="el" href="struct_m_d_m_a___init_type_def.html#a99e68173d73b314e7d8c27aa859b1dc8">MDMA_InitTypeDef</a></li>
<li>SourceDataSize&#160;:&#160;<a class="el" href="struct_m_d_m_a___init_type_def.html#ad6808b8ff46e3158c967f6fd08b44561">MDMA_InitTypeDef</a></li>
<li>SourceInc&#160;:&#160;<a class="el" href="struct_m_d_m_a___init_type_def.html#a810940b74cb3c79b3e7a761286038afc">MDMA_InitTypeDef</a></li>
<li>SpdifrxClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#a81e564d3954f5d4ba3aa43b8d93197e9">RCC_PeriphCLKInitTypeDef</a></li>
<li>Speed&#160;:&#160;<a class="el" href="struct_g_p_i_o___init_type_def.html#aae3b8ba407fb4f974cbce9cc03fc189d">GPIO_InitTypeDef</a></li>
<li>Spi123ClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#a01e364295489287fd64d3a765aa6201e">RCC_PeriphCLKInitTypeDef</a></li>
<li>Spi45ClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#af80ddc76501089bdcb8ce7ab6f298711">RCC_PeriphCLKInitTypeDef</a></li>
<li>Spi6ClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#a07471475d17c54062fd753d0c21fb29a">RCC_PeriphCLKInitTypeDef</a></li>
<li>SPPR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga12f79d4e3ddc69893ba8bff890d04cc5">TPI_Type</a></li>
<li>SPSEL&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type</a></li>
<li>SQR1&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a0185aa54962ba987f192154fb7a2d673">ADC_TypeDef</a></li>
<li>SQR2&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a6b6e55e6c667042e5a46a76518b73d5a">ADC_TypeDef</a></li>
<li>SQR3&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#a51dbdba74c4d3559157392109af68fc6">ADC_TypeDef</a></li>
<li>SQR4&#160;:&#160;<a class="el" href="struct_a_d_c___type_def.html#ab66c9816c1ca151a6ec728ec55655264">ADC_TypeDef</a></li>
<li>SR&#160;:&#160;<a class="el" href="struct_c_o_m_p_o_p_t___type_def.html#a1c92fb777221172c124fdc54a028bfee">COMPOPT_TypeDef</a>, <a class="el" href="struct_d_a_c___type_def.html#a1d3fd83d6ed8b2d90b471db4509b0e70">DAC_TypeDef</a>, <a class="el" href="struct_d_c_m_i___type_def.html#a1bbe4b3cc5d9552526bec462b42164d5">DCMI_TypeDef</a>, <a class="el" href="struct_d_t_s___type_def.html#a394860e24d1f493911e31943e6d22c64">DTS_TypeDef</a>, <a class="el" href="struct_f_m_a_c___type_def.html#a4db0532c8e24b84f1c7501a5374a40d6">FMAC_TypeDef</a>, <a class="el" href="struct_f_m_c___bank3___type_def.html#a43af4c901144f747741adbf1a479586a">FMC_Bank3_TypeDef</a>, <a class="el" href="struct_i_w_d_g___type_def.html#a9bbfbe921f2acfaf58251849bd0a511c">IWDG_TypeDef</a>, <a class="el" href="struct_o_c_t_o_s_p_i___type_def.html#af2d07941b01f96222d175a411a99cbc5">OCTOSPI_TypeDef</a>, <a class="el" href="struct_p_s_s_i___type_def.html#a9e0917888f230c3b231be7a55ab40f13">PSSI_TypeDef</a>, <a class="el" href="struct_r_a_m_e_c_c___monitor_type_def.html#a65365b831054071c8b1d901e96d76298">RAMECC_MonitorTypeDef</a>, <a class="el" href="struct_r_n_g___type_def.html#a4e4c38cd6a078fea5f9fa5e31bc0d326">RNG_TypeDef</a>, <a class="el" href="struct_s_a_i___block___type_def.html#ad1505a32bdca9a2f8da708c7372cdafc">SAI_Block_TypeDef</a>, <a class="el" href="struct_s_p_d_i_f_r_x___type_def.html#ad3ff338b3b53a2d26d0154b0037e2a20">SPDIFRX_TypeDef</a>, <a class="el" href="struct_s_p_i___type_def.html#a33f3dd6a505d06fe6c466b63be451891">SPI_TypeDef</a>, <a class="el" href="struct_t_i_m___type_def.html#acedfc978c879835c05ef1788ad26b2ff">TIM_TypeDef</a>, <a class="el" href="struct_w_w_d_g___type_def.html#a15655cda4854cc794db1f27b3c0bba38">WWDG_TypeDef</a></li>
<li>SR1&#160;:&#160;<a class="el" href="struct_f_l_a_s_h___type_def.html#a5d830598943ff82b6be4ea8fc6c9bac8">FLASH_TypeDef</a></li>
<li>SR2&#160;:&#160;<a class="el" href="struct_f_m_c___bank2___type_def.html#a457388fbdc292927afa844272ad00782">FMC_Bank2_TypeDef</a></li>
<li>SrcAddress&#160;:&#160;<a class="el" href="struct_m_d_m_a___link_node_conf_type_def.html#ac536fa7c94957127ebf16967b57e2159">MDMA_LinkNodeConfTypeDef</a></li>
<li>SRCR&#160;:&#160;<a class="el" href="struct_l_t_d_c___type_def.html#a502dd9d2d17025a90bdf968eb29827f2">LTDC_TypeDef</a></li>
<li>SSCR&#160;:&#160;<a class="el" href="struct_l_t_d_c___type_def.html#aa5bb98a48470eaf50559e916bce23278">LTDC_TypeDef</a></li>
<li>SSPSR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga037901d7cb870199ac51d9ad0ef9fd1a">TPI_Type</a></li>
<li>SSR&#160;:&#160;<a class="el" href="struct_r_t_c___type_def.html#aefbd38be87117d1fced289bf9c534414">RTC_TypeDef</a></li>
<li>STA&#160;:&#160;<a class="el" href="struct_s_d_m_m_c___type_def.html#a9bbd3a78b1a7fb30c53e1d17a31b9b32">SDMMC_TypeDef</a></li>
<li>stacksize&#160;:&#160;<a class="el" href="structos__thread__def.html#aa0dd2cff64a499a08f422dd159fe5780">os_thread_def</a></li>
<li>State&#160;:&#160;<a class="el" href="struct_____d_m_a___handle_type_def.html#a9759b676141bec799cdab94c3e08e6e4">__DMA_HandleTypeDef</a>, <a class="el" href="struct_____i2_c___handle_type_def.html#a3421cd62d9e34c4a5ff1706916c8ae7a">__I2C_HandleTypeDef</a>, <a class="el" href="struct_____m_d_m_a___handle_type_def.html#ae341d77e8a41b03d4540bd35a6b7f035">__MDMA_HandleTypeDef</a>, <a class="el" href="struct_____s_p_i___handle_type_def.html#aa3e13040cc9ea19050d21818bccd49c9">__SPI_HandleTypeDef</a>, <a class="el" href="struct_t_i_m___handle_type_def.html#a6b6eeaf94f2e6e3d0a5bdac44adf21d6">TIM_HandleTypeDef</a></li>
<li>state&#160;:&#160;<a class="el" href="structarm__pid__instance__f32.html#ac8ef2ec43648e986c99e1df96c68a36f">arm_pid_instance_f32</a>, <a class="el" href="structarm__pid__instance__q15.html#a3c54b074a2a3d1bbc2fe2589fcc25231">arm_pid_instance_q15</a>, <a class="el" href="structarm__pid__instance__q31.html#a57a7012c3c8c53f91dd3c1a3994e467a">arm_pid_instance_q31</a></li>
<li>stateIndex&#160;:&#160;<a class="el" href="structarm__fir__sparse__instance__f32.html#a57585aeca9dc8686e08df2865375a86d">arm_fir_sparse_instance_f32</a>, <a class="el" href="structarm__fir__sparse__instance__q15.html#a89487f28cab52637426024005e478985">arm_fir_sparse_instance_q15</a>, <a class="el" href="structarm__fir__sparse__instance__q31.html#a557ed9d477e76e4ad2019344f19f568a">arm_fir_sparse_instance_q31</a>, <a class="el" href="structarm__fir__sparse__instance__q7.html#a2d2e65473fe3a3f2b953b4e0b60824df">arm_fir_sparse_instance_q7</a></li>
<li>status&#160;:&#160;<a class="el" href="structos_event.html#aafcd2cedd08e033f9df25fd9875caaf2">osEvent</a></li>
<li>STIR&#160;:&#160;<a class="el" href="group___c_m_s_i_s__core___debug_functions.html#ga37de89637466e007171c6b135299bc75">NVIC_Type</a>, <a class="el" href="group___c_m_s_i_s__core___debug_functions.html#gad70825dd0869b7ccd07fb2b8680fcdb6">SCB_Type</a></li>
<li>StopBits&#160;:&#160;<a class="el" href="struct_u_a_r_t___init_type_def.html#a6717dfe595617c7b2d57139d9cd306ef">UART_InitTypeDef</a></li>
<li>StreamBaseAddress&#160;:&#160;<a class="el" href="struct_____d_m_a___handle_type_def.html#ab9250d33bdf9de7b87fa4325382518c4">__DMA_HandleTypeDef</a></li>
<li>StreamIndex&#160;:&#160;<a class="el" href="struct_____d_m_a___handle_type_def.html#a3ada2bc091757d7b92ab8ca70211ccae">__DMA_HandleTypeDef</a></li>
<li>supportVectors&#160;:&#160;<a class="el" href="structarm__svm__linear__instance__f32.html#ad1f056852be3926759e7f69ff87418e0">arm_svm_linear_instance_f32</a>, <a class="el" href="structarm__svm__polynomial__instance__f32.html#afa0b28fec2dae7737e626a1292ef442d">arm_svm_polynomial_instance_f32</a>, <a class="el" href="structarm__svm__rbf__instance__f32.html#a91f0c7dcfcc8aa65b6433c0e66c92062">arm_svm_rbf_instance_f32</a>, <a class="el" href="structarm__svm__sigmoid__instance__f32.html#a88273f8f9f9f28618a6a7890f9bc630e">arm_svm_sigmoid_instance_f32</a></li>
<li>Swap&#160;:&#160;<a class="el" href="struct_u_a_r_t___adv_feature_init_type_def.html#a1bc32023897ca98005319c4de7b84a1f">UART_AdvFeatureInitTypeDef</a></li>
<li>SWIER1&#160;:&#160;<a class="el" href="struct_e_x_t_i___type_def.html#af56898c09c0706ab0b5c19348396f5dd">EXTI_TypeDef</a></li>
<li>SWIER2&#160;:&#160;<a class="el" href="struct_e_x_t_i___type_def.html#ac537696dafad0997c5ebc4f4d21abd16">EXTI_TypeDef</a></li>
<li>SWIER3&#160;:&#160;<a class="el" href="struct_e_x_t_i___type_def.html#a46ae82f4486d865d15cd405c1c32a171">EXTI_TypeDef</a></li>
<li>Swpmi1ClockSelection&#160;:&#160;<a class="el" href="struct_r_c_c___periph_c_l_k_init_type_def.html#a3cd5d5af8e5f4ba742de80ee9abd19e6">RCC_PeriphCLKInitTypeDef</a></li>
<li>SWTRIGR&#160;:&#160;<a class="el" href="struct_d_a_c___type_def.html#a4ccb66068a1ebee1179574dda20206b6">DAC_TypeDef</a></li>
<li>SyncEnable&#160;:&#160;<a class="el" href="struct_h_a_l___d_m_a___mux_sync_config_type_def.html#a7b213a462174caf2f7ae69a0cea1e274">HAL_DMA_MuxSyncConfigTypeDef</a></li>
<li>SyncPolarity&#160;:&#160;<a class="el" href="struct_h_a_l___d_m_a___mux_sync_config_type_def.html#ab9358d892ba465e1e224533e5e2edc94">HAL_DMA_MuxSyncConfigTypeDef</a></li>
<li>SyncSignalID&#160;:&#160;<a class="el" href="struct_h_a_l___d_m_a___mux_sync_config_type_def.html#a94e5c09dc5fe0ae5088bb54be6a715fb">HAL_DMA_MuxSyncConfigTypeDef</a></li>
<li>SYSCLKDivider&#160;:&#160;<a class="el" href="struct_l_l___u_t_i_l_s___clk_init_type_def.html#a13f6fcf896f6a10c5333125de2cb399d">LL_UTILS_ClkInitTypeDef</a>, <a class="el" href="struct_r_c_c___clk_init_type_def.html#aa49663a5d76af14424c7d1c3525b9381">RCC_ClkInitTypeDef</a></li>
<li>SYSCLKSource&#160;:&#160;<a class="el" href="struct_r_c_c___clk_init_type_def.html#a4ceff1fdbf423e347c63052ca2c1d7e1">RCC_ClkInitTypeDef</a></li>
</ul>
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